With the advent of metal-gate on high-k gate dielectric process flows, Positive Bias Temperature Instability (PBTI) has become important for n-Channel MOS (NMOS). The magnitude of PBTI is about 70% the threshold voltage shift (ΔVt) of Negative Bias Temperature Instability (NBTI) in 20 nm gate length IC manufacturing process technologies.
A Static Random Access Memory (SRAM) is conventionally screened using Nwell reverse-body-bias (RBB) to effectively mimic p-channel MOS (PMOS) end-of-the-line (EOL) Vt degradation. SRAM capability to provide NMOS Driver/pass-gate (PG) transistor screening for PBTI EOL is also desired. A deep Nwell (DNwell)/Iso Pwell implant has been suggested for SRAMs to provide the added diode for back bias capability to allow screening NMOS driver transistors and PG transistors. The DNwell requires a separate mask pattern which is performed before gate dielectric and gate electrode formation. The separate masking level required for the DNwell adds to cost and cycle time.